[Oral Presentation]Selective Harmonic Elimination Control for Cascaded Digital Power Amplifier

Selective Harmonic Elimination Control for Cascaded Digital Power Amplifier
ID:253 Submission ID:1752 View Protection:ATTENDEE Updated Time:2020-10-15 21:00:47 Hits:288 Oral Presentation

Start Time:2020-11-04 09:45 (Asia/Shanghai)

Duration:15min

Session:[B] Power Electronics Technology and Application » [B3] Session 23 and Session 28

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Abstract
In this paper, the selective harmonic elimination (SHE) strategy for cascaded digital power amplifier is derived and proposed. To solve the problem of slow iteration speed or even non-convergence of the traditional iterative method when the number of levels or the number of harmonic elimination equations is large, a new solution method based on "interior point method” is introduced. In practical application the dead-time cannot be avoided, so the impact of dead-time on selective harmonic elimination strategy is also analyzed. Based on the relationship between output voltage and current during dead-time, the control method of “flexible insertion of dead-time on line” is proposed, which can significantly weaken the dead-time effect on selective harmonic elimination strategy in practice.
Keywords
selective harmonic elimination, interior point method, dead-time effect elimination
Speaker
Junyao Tu
Huazhong University of Science and Technology

Submission Author
Junyao Tu Huazhong University of Science and Technology
Hengyang Liu Huazhong University of Science and Technology
Wubin Kong Huazhong University of Science and Technology;State Key Laboratory of Advanced Electromagnetic Engineering and Technology
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